EMI-Resilient Amplifier Circuits by Marcel J. Horst Wouter A. Serdijn & André C. Linnenbank

Author:Marcel J. Horst, Wouter A. Serdijn & André C. Linnenbank
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

4.6.3 Transistor Matching

An elaborate treatise of device mismatch modelling in differential stages is beyond the scope of this work. The interested reader is revered to specialized literature, e.g., Papathanasiou (2006). This subsection will only present some general ways to improve device matching.

In general, differences between devices can be kept small by giving them large (effective) areas. For instance, the differences in saturation current , and therefore differences in or , can be made small by making the emitter areas relatively large with respect to the mask inaccuracies. Placing devices close to one another and giving them the same orientation is also beneficial to minimize differences between them. Common centroid layout (Papathanasiou 2006; Gray et al. 2001) will often also reduce mismatch, since it is possible to ensure that both devices share the same centroid and that they are symmetrical.

Mismatch in mosfets is related to an area term (Lovett et al. 1998), with and being the width and length of the mosfet, respectively. A large area thus improves transistor matching. It should be noted, however, than in case of (and ) mismatch for equal area devices, a wide channel device with short channel length (large ratio) has poorer matching than an equal area narrow channel transistor with relatively long channel length (small ratio). This difference in matching can be as much as 300 (Lovett et al. 1998). Also, it seems to be beneficial to bias submicron mosfets at such a high voltage that velocity saturation occurs. Due to this ‘intrinsic feedback mechanism’, less current mismatch than predicted by occurs (Bastos et al. 1997). Biasing in this region has, however, other drawbacks as discussed in Chap. 3.

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